The present invention relates to a phase change memory device and a method for manufacturing the same, and more particularly, to a phase change memory device which enables manufacturing of a highly integrated phase change memory device having stable reset resistance and a method for manufacturing the same.
Memory devices are typically classified into two categories: volatile random access memory (RAM), which loses inputted information when power is interrupted; and non-volatile read-only memory (ROM), which can continuously maintain the stored state of inputted information even when power is interrupted. Examples of volatile RAM include dynamic RAM (DRAM) and static RAM (SRAM), and examples of non-volatile ROM include flash memory devices such as an electrically erasable and programmable ROM (EEPROM).
Although DRAM is an excellent memory device, the DRAM requires a high charge storing capacity, which in turn requires the surface area of an electrode to increase. When the surface area of the electrode is increased, high levels of integration become difficult. Further, in flash memory devices, two gates are stacked upon each other. Accordingly, an operation voltage that is higher than a power source voltage is required, and thus. In order to provide the high operation voltage, a separate booster circuit is needed to supply the voltage required for write and delete operations. All of these factors present difficulties when attempting to accomplish high levels of integration.
Under these situations, the so-called phase change memory device drew attention for research in an effort to develop a memory device having a simple configuration that is capable of accomplishing a high level of integration while retaining the characteristics of a non-volatile memory device. In the phase change memory device, a phase change from a crystalline state to an amorphous state occurs in a phase change layer interposed between a bottom electrode and a top electrode due to a current flow between the bottom electrode and the top electrode. The information stored in a cell is recognized utilizing the difference in resistance between the crystalline state and the amorphous state of the phase change layer.
In detail, in the phase change memory device, the phase change layer undergoes a phase change between a set state, being the crystalline state, and a reset state, being the amorphous state. This phase change occurs by heat (that is, Joule heat) generated by an applied current. The resistance of the phase change layer in the amorphous state is higher than the resistance of the phase change layer in the crystalline state, as such whether the information stored in a phase change memory cell has a logic ‘1’ or a logic ‘0’ can be determined by sensing the current flowing through the phase change layer in a read mode.
One of the most important factors when developing a highly integrated phase change memory device is to secure a programming current. One way of securing the programming current includes the utilization of a vertical type PN diode as a switching element.
FIG. 1 is a cross-sectional view showing a conventional phase change memory device which adopts a PN diode.
Referring to FIG. 1, an N-type impurity region 110 is formed on the surface of a silicon substrate 100. A stack pattern 140 of an N-type silicon layer and a P-type silicon layer is formed on the N-type impurity region 110, and the stack pattern 140 and the N-type impurity region 110 constitute a PN diode 150. A heater 170 serving as a bottom electrode is formed on the stack pattern 140 of the N-type silicon layer and the P-type silicon layer, and a phase change layer 180 is formed on the heater 170.
The phase change memory device having the PN diode as a switching element has an improved current flow characteristic compared to a phase change memory device utilizing a CMOS transistor as a switching element. Therefore, in the PN diode phase change memory device it is possible to decrease the cell size when compared to a DRAM or a flash memory device.
In the phase change memory device, when implementing reset programming for changing the phase of the phase change layer from the crystalline state to the amorphous state to allow the phase change layer to have a high reset resistance, the phase change layer undergoes melting and cooling procedures.
In a conventional phase change memory device, the heat generated by the reset current (which is transferred from the heater to the phase change layer) does not cool quickly. If when implementing the reset programming, the cooling of the phase change layer is not done quickly, a portion of the phase change layer will change to a phase between the amorphous state and the crystalline state, and a phenomenon, in which reset resistance decreases, occurs.
Accordingly, in a conventional phase change memory device, when the heat transferred from the heater to the phase change layer is not quickly cooled, the phase change layer will not have a stable reset resistance, resulting in a poor sensing margin in the phase change memory device, and thus concerns emerge regarding the reliability of the conventional phase change memory device.